Home
last modified time | relevance | path

Searched refs:regSH_MEM_BASES (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v11.c87 WREG32(SOC15_REG_OFFSET(GC, 0, regSH_MEM_BASES), sh_mem_bases); in program_sh_mem_settings_v11()
H A Dgfx_v9_4_3.c1261 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); in gfx_v9_4_3_xcc_init_compute_vmid()
1321 regSH_MEM_BASES, 0); in gfx_v9_4_3_xcc_constants_init()
1336 regSH_MEM_BASES, tmp); in gfx_v9_4_3_xcc_constants_init()
H A Dgfx_v12_0.c1687 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); in gfx_v12_0_init_compute_vmid()
1732 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); in gfx_v12_0_constants_init()
H A Dgfx_v11_0.c1948 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); in gfx_v11_0_init_compute_vmid()
2034 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); in gfx_v11_0_constants_init()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h418 #define regSH_MEM_BASES … macro
H A Dgc_9_4_2_offset.h6112 #define regSH_MEM_BASES … macro
H A Dgc_11_5_0_offset.h5105 #define regSH_MEM_BASES … macro
H A Dgc_12_0_0_offset.h9259 #define regSH_MEM_BASES … macro
H A Dgc_11_0_3_offset.h6562 #define regSH_MEM_BASES … macro
H A Dgc_11_0_0_offset.h6282 #define regSH_MEM_BASES … macro