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Searched refs:regSH_MEM_BASES (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c1175 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); in gfx_v9_4_3_xcc_init_compute_vmid()
1251 regSH_MEM_BASES, 0); in gfx_v9_4_3_xcc_constants_init()
1266 regSH_MEM_BASES, tmp); in gfx_v9_4_3_xcc_constants_init()
H A Dgfx_v12_1.c1731 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); in gfx_v12_1_xcc_init_compute_vmid()
1788 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, tmp); in gfx_v12_1_xcc_constants_init()
H A Dgfx_v12_0.c1804 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); in gfx_v12_0_init_compute_vmid()
1864 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); in gfx_v12_0_constants_init()
H A Dgfx_v11_0.c2130 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); in gfx_v11_0_init_compute_vmid()
2225 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); in gfx_v11_0_constants_init()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h418 #define regSH_MEM_BASES … macro
H A Dgc_9_4_2_offset.h6112 #define regSH_MEM_BASES … macro
H A Dgc_12_0_0_offset.h9259 #define regSH_MEM_BASES … macro
H A Dgc_11_0_3_offset.h6562 #define regSH_MEM_BASES … macro
H A Dgc_11_0_0_offset.h6282 #define regSH_MEM_BASES … macro