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Searched refs:regSH_MEM_BASES (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v11.c87 WREG32(SOC15_REG_OFFSET(GC, 0, regSH_MEM_BASES), sh_mem_bases); in program_sh_mem_settings_v11()
H A Dgfx_v9_4_3.c1180 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); in gfx_v9_4_3_xcc_init_compute_vmid()
1256 regSH_MEM_BASES, 0); in gfx_v9_4_3_xcc_constants_init()
1271 regSH_MEM_BASES, tmp); in gfx_v9_4_3_xcc_constants_init()
H A Dgfx_v12_1.c1547 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); in gfx_v12_1_sw_init()
1598 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, tmp); in gfx_v12_1_sw_fini()
H A Dgfx_v12_0.c1815 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); in gfx_v12_0_tcp_harvest()
1875 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); in gfx_v12_0_get_cpg_int_cntl()
H A Dgfx_v11_0.c2174 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases);
2269 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); in gfx_v11_0_get_cpc_int_cntl()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h418 #define regSH_MEM_BASES … macro
H A Dgc_9_4_2_offset.h6112 #define regSH_MEM_BASES … macro
H A Dgc_12_0_0_offset.h9259 #define regSH_MEM_BASES … macro
H A Dgc_11_0_3_offset.h6562 #define regSH_MEM_BASES … macro
H A Dgc_11_0_0_offset.h6282 #define regSH_MEM_BASES … macro