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Searched refs:regSDMA1_RLC_CGCG_CTRL (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c5648 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5650 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5682 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5684 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
H A Dgfx_v12_0.c4240 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); in gfx_v12_0_update_coarse_grain_clock_gating()
4242 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); in gfx_v12_0_update_coarse_grain_clock_gating()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_12_0_0_offset.h1122 #define regSDMA1_RLC_CGCG_CTRL … macro
H A Dgc_11_0_3_offset.h1008 #define regSDMA1_RLC_CGCG_CTRL … macro
H A Dgc_11_0_0_offset.h1002 #define regSDMA1_RLC_CGCG_CTRL … macro