Home
last modified time | relevance | path

Searched refs:regSDMA1_QUEUE5_RB_WPTR_BASE_IDX (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_12_0_0_offset.h1645 #define regSDMA1_QUEUE5_RB_WPTR_BASE_IDX … macro
H A Dgc_11_0_3_offset.h1495 #define regSDMA1_QUEUE5_RB_WPTR_BASE_IDX … macro
H A Dgc_11_0_0_offset.h1483 #define regSDMA1_QUEUE5_RB_WPTR_BASE_IDX … macro