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Searched refs:regSDMA1_QUEUE0_MIDCMD_DATA5_BASE_IDX (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_12_0_0_offset.h1235 #define regSDMA1_QUEUE0_MIDCMD_DATA5_BASE_IDX … macro
H A Dgc_11_0_3_offset.h1127 #define regSDMA1_QUEUE0_MIDCMD_DATA5_BASE_IDX … macro
H A Dgc_11_0_0_offset.h1115 #define regSDMA1_QUEUE0_MIDCMD_DATA5_BASE_IDX … macro