Searched refs:regSDMA0_WATCHDOG_CNTL (Results 1 – 6 of 6) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | sdma_v6_0.c | 569 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL)); in sdma_v6_0_gfx_resume()
573 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL), temp); in sdma_v6_0_gfx_resume()
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| H A D | sdma_v7_0.c | 593 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL)); in sdma_v7_0_gfx_resume()
597 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL), tmp); in sdma_v7_0_gfx_resume()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_11_5_0_offset.h | 76 #define regSDMA0_WATCHDOG_CNTL … macro
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| H A D | gc_12_0_0_offset.h | 70 #define regSDMA0_WATCHDOG_CNTL … macro
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| H A D | gc_11_0_3_offset.h | 74 #define regSDMA0_WATCHDOG_CNTL … macro
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| H A D | gc_11_0_0_offset.h | 74 #define regSDMA0_WATCHDOG_CNTL … macro
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