Searched refs:regSDMA0_UTCL1_CNTL (Results 1 – 7 of 7) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | sdma_v7_0.c | 600 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL)); in sdma_v7_0_gfx_resume()
603 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), tmp); in sdma_v7_0_gfx_resume()
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| H A D | sdma_v6_0.c | 582 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL)); in sdma_v6_0_gfx_resume_instance()
585 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp); in sdma_v6_0_gfx_resume_instance()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/sdma/ |
| H A D | sdma_4_4_0_offset.h | 105 #define regSDMA0_UTCL1_CNTL … macro
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_11_5_0_offset.h | 100 #define regSDMA0_UTCL1_CNTL … macro
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| H A D | gc_12_0_0_offset.h | 90 #define regSDMA0_UTCL1_CNTL … macro
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| H A D | gc_11_0_3_offset.h | 98 #define regSDMA0_UTCL1_CNTL … macro
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| H A D | gc_11_0_0_offset.h | 98 #define regSDMA0_UTCL1_CNTL … macro
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