Home
last modified time | relevance | path

Searched refs:regSDMA0_QUEUE5_MIDCMD_DATA1 (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_5_0_offset.h689 #define regSDMA0_QUEUE5_MIDCMD_DATA1 … macro
H A Dgc_12_0_0_offset.h714 #define regSDMA0_QUEUE5_MIDCMD_DATA1 … macro
H A Dgc_11_0_3_offset.h690 #define regSDMA0_QUEUE5_MIDCMD_DATA1 … macro
H A Dgc_11_0_0_offset.h684 #define regSDMA0_QUEUE5_MIDCMD_DATA1 … macro