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Searched refs:regSDMA0_QUEUE1_RB_WPTR (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v7_0.c93 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR),
H A Dsdma_v6_0.c93 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR),
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_5_0_offset.h291 #define regSDMA0_QUEUE1_RB_WPTR … macro
H A Dgc_12_0_0_offset.h286 #define regSDMA0_QUEUE1_RB_WPTR … macro
H A Dgc_11_0_3_offset.h292 #define regSDMA0_QUEUE1_RB_WPTR … macro
H A Dgc_11_0_0_offset.h286 #define regSDMA0_QUEUE1_RB_WPTR … macro