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Searched refs:regSDMA0_QUEUE0_RB_CNTL (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v11.c135 regSDMA0_QUEUE0_RB_CNTL) - regSDMA0_QUEUE0_RB_CNTL; in get_sdma_rlc_reg_offset()
139 regSDMA1_QUEUE0_RB_CNTL) - regSDMA0_QUEUE0_RB_CNTL; in get_sdma_rlc_reg_offset()
146 + queue_id * (regSDMA0_QUEUE1_RB_CNTL - regSDMA0_QUEUE0_RB_CNTL); in get_sdma_rlc_reg_offset()
358 WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL, in hqd_sdma_load_v11()
408 WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL, data); in hqd_sdma_load_v11()
427 for (reg = regSDMA0_QUEUE0_RB_CNTL; in hqd_sdma_dump_v11()
480 sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL); in hqd_sdma_is_occupied_v11()
547 temp = RREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL); in hqd_sdma_destroy_v11()
549 WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL, temp); in hqd_sdma_destroy_v11()
563 WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL, in hqd_sdma_destroy_v11()
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H A Damdgpu_amdkfd_gfx_v12.c86 regSDMA0_QUEUE0_RB_CNTL) - regSDMA0_QUEUE0_RB_CNTL; in get_sdma_rlc_reg_offset()
90 regSDMA1_QUEUE0_RB_CNTL) - regSDMA0_QUEUE0_RB_CNTL; in get_sdma_rlc_reg_offset()
97 + queue_id * (regSDMA0_QUEUE1_RB_CNTL - regSDMA0_QUEUE0_RB_CNTL); in get_sdma_rlc_reg_offset()
144 const uint32_t first_reg = regSDMA0_QUEUE0_RB_CNTL; in hqd_sdma_dump_v12()
H A Dsdma_v6_0.c77 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_CNTL),
399 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); in sdma_v6_0_gfx_stop()
401 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); in sdma_v6_0_gfx_stop()
498 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); in sdma_v6_0_gfx_resume()
506 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); in sdma_v6_0_gfx_resume()
600 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); in sdma_v6_0_gfx_resume()
H A Dsdma_v7_0.c77 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_CNTL),
431 rb_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); in sdma_v7_0_gfx_stop()
433 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); in sdma_v7_0_gfx_stop()
519 rb_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); in sdma_v7_0_gfx_resume()
527 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); in sdma_v7_0_gfx_resume()
623 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); in sdma_v7_0_gfx_resume()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_5_0_offset.h195 #define regSDMA0_QUEUE0_RB_CNTL … macro
H A Dgc_12_0_0_offset.h182 #define regSDMA0_QUEUE0_RB_CNTL … macro
H A Dgc_11_0_3_offset.h196 #define regSDMA0_QUEUE0_RB_CNTL … macro
H A Dgc_11_0_0_offset.h190 #define regSDMA0_QUEUE0_RB_CNTL … macro