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Searched refs:regSDMA0_QUEUE0_DOORBELL (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v11.c378 WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_DOORBELL, data); in hqd_sdma_load_v11()
431 reg <= regSDMA0_QUEUE0_DOORBELL; reg++) in hqd_sdma_dump_v11()
562 WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_DOORBELL, 0); in hqd_sdma_destroy_v11()
H A Dsdma_v6_0.c544 doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL)); in sdma_v6_0_gfx_resume()
554 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell); in sdma_v6_0_gfx_resume()
H A Dsdma_v7_0.c568 doorbell = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL)); in sdma_v7_0_gfx_resume()
578 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell); in sdma_v7_0_gfx_resume()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_5_0_offset.h229 #define regSDMA0_QUEUE0_DOORBELL … macro
H A Dgc_12_0_0_offset.h212 #define regSDMA0_QUEUE0_DOORBELL … macro
H A Dgc_11_0_3_offset.h230 #define regSDMA0_QUEUE0_DOORBELL … macro
H A Dgc_11_0_0_offset.h224 #define regSDMA0_QUEUE0_DOORBELL … macro