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Searched refs:regSCRATCH_REG0 (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c431 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); in gfx_v9_4_3_ring_test_ring()
432 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); in gfx_v9_4_3_ring_test_ring()
1433 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
H A Dgfx_v12_0.c406 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); in gfx_v12_0_ring_test_ring()
701 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); in gfx_v12_0_init_rlcg_reg_access_ctrl()
H A Dgfx_v11_0.c509 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); in gfx_v11_0_ring_test_ring()
880 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); in gfx_v11_0_init_rlcg_reg_access_ctrl()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h5036 #define regSCRATCH_REG0 … macro
H A Dgc_9_4_2_offset.h2818 #define regSCRATCH_REG0 … macro
H A Dgc_11_5_0_offset.h5683 #define regSCRATCH_REG0 … macro
H A Dgc_12_0_0_offset.h4348 #define regSCRATCH_REG0 … macro
H A Dgc_11_0_3_offset.h7216 #define regSCRATCH_REG0 … macro
H A Dgc_11_0_0_offset.h6916 #define regSCRATCH_REG0 … macro