Searched refs:regRLC_SPM_MC_CNTL (Results 1 – 9 of 9) sorted by relevance
/linux/drivers/gpu/drm/amd/amdgpu/ |
H A D | gfx_v12_0.c | 3792 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); in gfx_v12_0_set_powergating_state() 3802 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); in gfx_v12_0_set_powergating_state() 3804 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); in gfx_v12_0_set_powergating_state() 3810 uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); in gfx_v12_0_update_coarse_grain_clock_gating()
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H A D | gfx_v9_4_3.c | 1641 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL); in gfx_v9_4_3_xcc_mqd_init() 1652 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); in gfx_v9_4_3_xcc_mqd_init() 1654 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); in gfx_v9_4_3_xcc_mqd_init()
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H A D | gfx_v11_0.c | 5326 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); in gfx_v11_0_set_powergating_state() 5337 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); in gfx_v11_0_set_powergating_state() 5339 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); in gfx_v11_0_set_powergating_state()
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/linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
H A D | gc_9_4_3_offset.h | 6560 #define regRLC_SPM_MC_CNTL … macro
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H A D | gc_9_4_2_offset.h | 5046 #define regRLC_SPM_MC_CNTL … macro
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H A D | gc_11_5_0_offset.h | 9009 #define regRLC_SPM_MC_CNTL … macro
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H A D | gc_12_0_0_offset.h | 7019 #define regRLC_SPM_MC_CNTL … macro
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H A D | gc_11_0_3_offset.h | 11198 #define regRLC_SPM_MC_CNTL … macro
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H A D | gc_11_0_0_offset.h | 10578 #define regRLC_SPM_MC_CNTL … macro
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