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Searched refs:regRLC_SPARE_INT_0 (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_12_0_0_offset.h7041 #define regRLC_SPARE_INT_0 … macro
H A Dgc_11_0_3_offset.h11220 #define regRLC_SPARE_INT_0 … macro
H A Dgc_11_0_0_offset.h10600 #define regRLC_SPARE_INT_0 … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v12_0.c742 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); in gfx_v12_0_init_rlcg_reg_access_ctrl()