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Searched refs:regRLC_PG_CNTL (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c2280 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); in gfx_v11_0_rlc_smu_handshake_cntl()
2294 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); in gfx_v11_0_rlc_start()
2483 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); in gfx_v11_0_rlc_resume()
5632 u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); in gfx_v11_cntl_power_gating()
5639 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data); in gfx_v11_cntl_power_gating()
H A Dgfx_v12_0.c1939 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); in gfx_v12_0_rlc_smu_handshake_cntl()
1953 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); in gfx_v12_0_rlc_start()
2092 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); in gfx_v12_0_rlc_resume()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h6480 #define regRLC_PG_CNTL … macro
H A Dgc_9_4_2_offset.h4968 #define regRLC_PG_CNTL … macro
H A Dgc_12_0_0_offset.h6390 #define regRLC_PG_CNTL … macro
H A Dgc_11_0_3_offset.h10490 #define regRLC_PG_CNTL … macro
H A Dgc_11_0_0_offset.h9888 #define regRLC_PG_CNTL … macro