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Searched refs:regRLC_MEM_SLP_CNTL (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c2736 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); in gfx_v9_4_3_xcc_update_medium_grain_clock_gating()
2739 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); in gfx_v9_4_3_xcc_update_medium_grain_clock_gating()
2762 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); in gfx_v9_4_3_xcc_update_medium_grain_clock_gating()
2765 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); in gfx_v9_4_3_xcc_update_medium_grain_clock_gating()
2923 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL)); in gfx_v9_4_3_get_clockgating_state()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h6400 #define regRLC_MEM_SLP_CNTL … macro
H A Dgc_9_4_2_offset.h4894 #define regRLC_MEM_SLP_CNTL … macro
H A Dgc_12_0_0_offset.h6762 #define regRLC_MEM_SLP_CNTL … macro
H A Dgc_11_0_3_offset.h10914 #define regRLC_MEM_SLP_CNTL … macro
H A Dgc_11_0_0_offset.h10302 #define regRLC_MEM_SLP_CNTL … macro