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Searched refs:regRLC_CP_SCHEDULERS (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v11.c187 value = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_CP_SCHEDULERS)); in hqd_load_v11()
190 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_CP_SCHEDULERS), value); in hqd_load_v11()
H A Dmes_v11_0.c1505 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); in mes_v11_0_kiq_setting()
1508 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); in mes_v11_0_kiq_setting()
1516 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); in mes_v11_0_kiq_clear()
1518 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); in mes_v11_0_kiq_clear()
H A Dmes_v12_0.c1610 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); in mes_v12_0_kiq_setting()
1613 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); in mes_v12_0_kiq_setting()
H A Dgfx_v12_0.c2856 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); in gfx_v12_0_kiq_setting()
2859 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); in gfx_v12_0_kiq_setting()
3670 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); in gfx_v12_0_hw_fini()
3672 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); in gfx_v12_0_hw_fini()
H A Dgfx_v9_4_3.c1796 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); in gfx_v9_4_3_xcc_kiq_setting()
1799 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp | 0x80); in gfx_v9_4_3_xcc_kiq_setting()
H A Dgfx_v11_0.c3927 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); in gfx_v11_0_kiq_setting()
3930 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); in gfx_v11_0_kiq_setting()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h6646 #define regRLC_CP_SCHEDULERS … macro
H A Dgc_9_4_2_offset.h5128 #define regRLC_CP_SCHEDULERS … macro
H A Dgc_11_5_0_offset.h9025 #define regRLC_CP_SCHEDULERS … macro
H A Dgc_12_0_0_offset.h7035 #define regRLC_CP_SCHEDULERS … macro
H A Dgc_11_0_3_offset.h11214 #define regRLC_CP_SCHEDULERS … macro
H A Dgc_11_0_0_offset.h10594 #define regRLC_CP_SCHEDULERS … macro