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Searched refs:regRLC_CP_SCHEDULERS (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmes_v11_0.c1557 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); in mes_v11_0_kiq_setting()
1560 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); in mes_v11_0_kiq_setting()
1568 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); in mes_v11_0_kiq_clear()
1570 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); in mes_v11_0_kiq_clear()
H A Dmes_v12_0.c1736 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); in mes_v12_0_kiq_setting()
1739 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); in mes_v12_0_kiq_setting()
H A Dgfx_v12_0.c2942 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); in gfx_v12_0_kiq_setting()
2945 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); in gfx_v12_0_kiq_setting()
3767 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); in gfx_v12_0_hw_fini()
3769 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); in gfx_v12_0_hw_fini()
H A Dgfx_v11_0.c4047 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); in gfx_v11_0_kiq_setting()
4050 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); in gfx_v11_0_kiq_setting()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h6646 #define regRLC_CP_SCHEDULERS … macro
H A Dgc_9_4_2_offset.h5128 #define regRLC_CP_SCHEDULERS … macro
H A Dgc_12_0_0_offset.h7035 #define regRLC_CP_SCHEDULERS … macro
H A Dgc_11_0_3_offset.h11214 #define regRLC_CP_SCHEDULERS … macro
H A Dgc_11_0_0_offset.h10594 #define regRLC_CP_SCHEDULERS … macro