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Searched refs:regRLC_CNTL (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v12_1.c1268 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); in gfx_v12_1_rlc_backdoor_autoload_enable()
1855 u32 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CNTL); in gfx_v12_1_xcc_rlc_stop()
1858 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CNTL, tmp); in gfx_v12_1_xcc_rlc_stop()
3295 rlc_cntl = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); in gfx_v12_1_is_rlc_enabled()
H A Dgfx_v9_4_3.c1337 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); in gfx_v9_4_3_is_rlc_enabled()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h6392 #define regRLC_CNTL macro
H A Dgc_9_4_2_offset.h4888 #define regRLC_CNTL macro
H A Dgc_12_0_0_offset.h6298 #define regRLC_CNTL macro
H A Dgc_11_0_3_offset.h10402 #define regRLC_CNTL macro
H A Dgc_11_0_0_offset.h9800 #define regRLC_CNTL macro