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Searched refs:regRLC_CGCG_CGLS_CTRL (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v12_1.c1751 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); in gfx_v12_1_xcc_rlc_resume()
3094 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); in gfx_v12_1_xcc_update_coarse_grain_clock_gating()
3110 regRLC_CGCG_CGLS_CTRL, data); in gfx_v12_1_xcc_update_coarse_grain_clock_gating()
3131 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); in gfx_v12_1_xcc_update_coarse_grain_clock_gating()
3140 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); in gfx_v12_1_xcc_update_coarse_grain_clock_gating()
3311 data = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL); in gfx_v12_1_get_clockgating_state()
H A Dgfx_v12_0.c2096 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); in gfx_v12_0_rlc_resume()
4109 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v12_0_update_coarse_grain_clock_gating()
4124 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); in gfx_v12_0_update_coarse_grain_clock_gating()
4173 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v12_0_update_coarse_grain_clock_gating()
4182 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); in gfx_v12_0_update_coarse_grain_clock_gating()
4343 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v12_0_get_clockgating_state()
H A Dgfx_v11_0.c2499 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); in gfx_v11_0_rlc_resume()
5525 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5540 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5589 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5598 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5826 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v11_0_get_clockgating_state()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h6488 #define regRLC_CGCG_CGLS_CTRL … macro
H A Dgc_9_4_2_offset.h4976 #define regRLC_CGCG_CGLS_CTRL … macro
H A Dgc_12_0_0_offset.h6400 #define regRLC_CGCG_CGLS_CTRL … macro
H A Dgc_11_0_3_offset.h10500 #define regRLC_CGCG_CGLS_CTRL … macro
H A Dgc_11_0_0_offset.h9898 #define regRLC_CGCG_CGLS_CTRL … macro