Searched refs:regRLC_CGCG_CGLS_CTRL (Results 1 – 6 of 6) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v12_0.c | 2089 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); in gfx_v12_0_rlc_resume()
4069 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v12_0_update_coarse_grain_clock_gating()
4084 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); in gfx_v12_0_update_coarse_grain_clock_gating()
4133 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v12_0_update_coarse_grain_clock_gating()
4142 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); in gfx_v12_0_update_coarse_grain_clock_gating()
4303 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v12_0_get_clockgating_state()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_4_3_offset.h | 6488 #define regRLC_CGCG_CGLS_CTRL … macro
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| H A D | gc_9_4_2_offset.h | 4976 #define regRLC_CGCG_CGLS_CTRL … macro
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| H A D | gc_12_0_0_offset.h | 6400 #define regRLC_CGCG_CGLS_CTRL … macro
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| H A D | gc_11_0_3_offset.h | 10500 #define regRLC_CGCG_CGLS_CTRL … macro
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| H A D | gc_11_0_0_offset.h | 9898 #define regRLC_CGCG_CGLS_CTRL … macro
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