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Searched refs:regPWRSEQ1_BL_PWM_CNTL2 (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_1_4_offset.h7204 #define regPWRSEQ1_BL_PWM_CNTL2 … macro
H A Ddpcs_4_2_3_offset.h126 #define regPWRSEQ1_BL_PWM_CNTL2 … macro
H A Ddpcs_4_2_2_offset.h109 #define regPWRSEQ1_BL_PWM_CNTL2 … macro
H A Ddpcs_4_2_0_offset.h122 #define regPWRSEQ1_BL_PWM_CNTL2 … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_5_offset.h12326 #define regPWRSEQ1_BL_PWM_CNTL2 … macro
H A Ddcn_3_5_1_offset.h10448 #define regPWRSEQ1_BL_PWM_CNTL2 … macro
H A Ddcn_3_5_0_offset.h10469 #define regPWRSEQ1_BL_PWM_CNTL2 … macro
H A Ddcn_3_1_4_offset.h11570 #define regPWRSEQ1_BL_PWM_CNTL2 … macro
H A Ddcn_3_1_2_offset.h12461 #define regPWRSEQ1_BL_PWM_CNTL2 … macro
H A Ddcn_3_1_6_offset.h13057 #define regPWRSEQ1_BL_PWM_CNTL2 … macro