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Searched refs:regPWRSEQ0_PWRSEQ_SPARE (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_1_4_offset.h7178 #define regPWRSEQ0_PWRSEQ_SPARE … macro
H A Ddpcs_4_2_3_offset.h100 #define regPWRSEQ0_PWRSEQ_SPARE … macro
H A Ddpcs_4_2_2_offset.h83 #define regPWRSEQ0_PWRSEQ_SPARE … macro
H A Ddpcs_4_2_0_offset.h96 #define regPWRSEQ0_PWRSEQ_SPARE … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_5_offset.h12300 #define regPWRSEQ0_PWRSEQ_SPARE … macro
H A Ddcn_3_5_1_offset.h10422 #define regPWRSEQ0_PWRSEQ_SPARE … macro
H A Ddcn_3_5_0_offset.h10443 #define regPWRSEQ0_PWRSEQ_SPARE … macro
H A Ddcn_3_1_4_offset.h11544 #define regPWRSEQ0_PWRSEQ_SPARE … macro
H A Ddcn_3_1_2_offset.h12435 #define regPWRSEQ0_PWRSEQ_SPARE … macro
H A Ddcn_3_1_6_offset.h13031 #define regPWRSEQ0_PWRSEQ_SPARE … macro