Home
last modified time | relevance | path

Searched refs:regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_1_4_offset.h7161 #define regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX … macro
H A Ddpcs_4_2_3_offset.h83 #define regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX … macro
H A Ddpcs_4_2_2_offset.h66 #define regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX … macro
H A Ddpcs_4_2_0_offset.h79 #define regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_5_offset.h12283 #define regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h10405 #define regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h10426 #define regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h11527 #define regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h12418 #define regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h13014 #define regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX … macro