Home
last modified time | relevance | path

Searched refs:regOTG3_OTG_DRR_CONTROL_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h8738 #define regOTG3_OTG_DRR_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h9351 #define regOTG3_OTG_DRR_CONTROL_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h7428 #define regOTG3_OTG_DRR_CONTROL_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h7449 #define regOTG3_OTG_DRR_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h8643 #define regOTG3_OTG_DRR_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h9596 #define regOTG3_OTG_DRR_CONTROL_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h8737 #define regOTG3_OTG_DRR_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h9820 #define regOTG3_OTG_DRR_CONTROL_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h9462 #define regOTG3_OTG_DRR_CONTROL_BASE_IDX … macro