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Searched refs:regOTG1_OTG_V_TOTAL_MID_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h8136 #define regOTG1_OTG_V_TOTAL_MID_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h8749 #define regOTG1_OTG_V_TOTAL_MID_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h6762 #define regOTG1_OTG_V_TOTAL_MID_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h6783 #define regOTG1_OTG_V_TOTAL_MID_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h8041 #define regOTG1_OTG_V_TOTAL_MID_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h8988 #define regOTG1_OTG_V_TOTAL_MID_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h8135 #define regOTG1_OTG_V_TOTAL_MID_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h9212 #define regOTG1_OTG_V_TOTAL_MID_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h8784 #define regOTG1_OTG_V_TOTAL_MID_BASE_IDX … macro