Home
last modified time | relevance | path

Searched refs:regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h8008 #define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h8619 #define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h6618 #define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h6639 #define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h7913 #define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h8858 #define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h8007 #define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h9082 #define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h8638 #define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX … macro