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Searched refs:regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h8004 #define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h8615 #define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h6614 #define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h6635 #define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h7909 #define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h8854 #define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h8003 #define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h9078 #define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h8634 #define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX … macro