Home
last modified time | relevance | path

Searched refs:regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h7972 #define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h8585 #define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h6582 #define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h6603 #define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h7877 #define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h8822 #define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h7971 #define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h9046 #define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h8602 #define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX … macro