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Searched refs:regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h5541 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B … macro
H A Ddcn_3_1_5_offset.h6998 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B … macro
H A Ddcn_3_5_1_offset.h12819 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B … macro
H A Ddcn_3_5_0_offset.h12840 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B … macro
H A Ddcn_3_1_4_offset.h13906 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B … macro
H A Ddcn_3_1_2_offset.h7239 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B … macro
H A Ddcn_3_2_1_offset.h5540 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B … macro
H A Ddcn_3_1_6_offset.h7459 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B … macro
H A Ddcn_4_1_0_offset.h6080 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B … macro