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Searched refs:regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h5371 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G … macro
H A Ddcn_3_1_5_offset.h6828 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G … macro
H A Ddcn_3_5_1_offset.h12649 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G … macro
H A Ddcn_3_5_0_offset.h12670 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G … macro
H A Ddcn_3_1_4_offset.h13736 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G … macro
H A Ddcn_3_1_2_offset.h7069 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G … macro
H A Ddcn_3_2_1_offset.h5370 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G … macro
H A Ddcn_3_1_6_offset.h7289 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G … macro
H A Ddcn_4_1_0_offset.h5910 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G … macro