Home
last modified time | relevance | path

Searched refs:regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h5185 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R … macro
H A Ddcn_3_1_5_offset.h6642 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R … macro
H A Ddcn_3_5_1_offset.h12463 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R … macro
H A Ddcn_3_5_0_offset.h12484 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R … macro
H A Ddcn_3_1_4_offset.h13550 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R … macro
H A Ddcn_3_1_2_offset.h6883 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R … macro
H A Ddcn_3_2_1_offset.h5184 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R … macro
H A Ddcn_3_1_6_offset.h7103 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R … macro
H A Ddcn_4_1_0_offset.h5724 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R … macro