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Searched refs:regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h5183 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G … macro
H A Ddcn_3_1_5_offset.h6640 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G … macro
H A Ddcn_3_5_1_offset.h12461 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G … macro
H A Ddcn_3_5_0_offset.h12482 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G … macro
H A Ddcn_3_1_4_offset.h13548 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G … macro
H A Ddcn_3_1_2_offset.h6881 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G … macro
H A Ddcn_3_2_1_offset.h5182 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G … macro
H A Ddcn_3_1_6_offset.h7101 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G … macro
H A Ddcn_4_1_0_offset.h5722 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G … macro