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Searched refs:regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h5071 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B … macro
H A Ddcn_3_1_5_offset.h6528 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B … macro
H A Ddcn_3_5_1_offset.h12349 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B … macro
H A Ddcn_3_5_0_offset.h12370 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B … macro
H A Ddcn_3_1_4_offset.h13436 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B … macro
H A Ddcn_3_1_2_offset.h6769 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B … macro
H A Ddcn_3_2_1_offset.h5070 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B … macro
H A Ddcn_3_1_6_offset.h6989 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B … macro
H A Ddcn_4_1_0_offset.h5610 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B … macro