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Searched refs:regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h5005 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R … macro
H A Ddcn_3_1_5_offset.h6462 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R … macro
H A Ddcn_3_5_1_offset.h12283 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R … macro
H A Ddcn_3_5_0_offset.h12304 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R … macro
H A Ddcn_3_1_4_offset.h13370 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R … macro
H A Ddcn_3_1_2_offset.h6703 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R … macro
H A Ddcn_3_2_1_offset.h5004 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R … macro
H A Ddcn_3_1_6_offset.h6923 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R … macro
H A Ddcn_4_1_0_offset.h5544 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R … macro