Home
last modified time | relevance | path

Searched refs:regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h5003 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G … macro
H A Ddcn_3_1_5_offset.h6460 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G … macro
H A Ddcn_3_5_1_offset.h12281 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G … macro
H A Ddcn_3_5_0_offset.h12302 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G … macro
H A Ddcn_3_1_4_offset.h13368 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G … macro
H A Ddcn_3_1_2_offset.h6701 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G … macro
H A Ddcn_3_2_1_offset.h5002 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G … macro
H A Ddcn_3_1_6_offset.h6921 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G … macro
H A Ddcn_4_1_0_offset.h5542 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G … macro