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Searched refs:regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h5022 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h6479 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h12300 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h12321 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h13387 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h6720 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h5021 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h6940 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h5561 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX … macro