Home
last modified time | relevance | path

Searched refs:regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h4904 #define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h6337 #define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h12251 #define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h12272 #define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h13339 #define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h6578 #define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h4903 #define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h6798 #define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h5427 #define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX … macro