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Searched refs:regMPCC1_MPCC_SM_CONTROL_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h4818 #define regMPCC1_MPCC_SM_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h6257 #define regMPCC1_MPCC_SM_CONTROL_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h12165 #define regMPCC1_MPCC_SM_CONTROL_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h12186 #define regMPCC1_MPCC_SM_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h13259 #define regMPCC1_MPCC_SM_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h6498 #define regMPCC1_MPCC_SM_CONTROL_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h4817 #define regMPCC1_MPCC_SM_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h6718 #define regMPCC1_MPCC_SM_CONTROL_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h5341 #define regMPCC1_MPCC_SM_CONTROL_BASE_IDX … macro