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Searched refs:regMPCC0_MPCC_UPDATE_LOCK_SEL (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h4785 #define regMPCC0_MPCC_UPDATE_LOCK_SEL … macro
H A Ddcn_3_1_5_offset.h6226 #define regMPCC0_MPCC_UPDATE_LOCK_SEL … macro
H A Ddcn_3_5_1_offset.h12132 #define regMPCC0_MPCC_UPDATE_LOCK_SEL … macro
H A Ddcn_3_5_0_offset.h12153 #define regMPCC0_MPCC_UPDATE_LOCK_SEL … macro
H A Ddcn_3_1_4_offset.h13228 #define regMPCC0_MPCC_UPDATE_LOCK_SEL … macro
H A Ddcn_3_1_2_offset.h6467 #define regMPCC0_MPCC_UPDATE_LOCK_SEL … macro
H A Ddcn_3_2_1_offset.h4784 #define regMPCC0_MPCC_UPDATE_LOCK_SEL … macro
H A Ddcn_3_1_6_offset.h6687 #define regMPCC0_MPCC_UPDATE_LOCK_SEL … macro
H A Ddcn_4_1_0_offset.h5308 #define regMPCC0_MPCC_UPDATE_LOCK_SEL … macro