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Searched refs:regMPCC0_MPCC_BG_R_CR (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h4795 #define regMPCC0_MPCC_BG_R_CR … macro
H A Ddcn_3_1_5_offset.h6234 #define regMPCC0_MPCC_BG_R_CR … macro
H A Ddcn_3_5_1_offset.h12142 #define regMPCC0_MPCC_BG_R_CR … macro
H A Ddcn_3_5_0_offset.h12163 #define regMPCC0_MPCC_BG_R_CR … macro
H A Ddcn_3_1_4_offset.h13236 #define regMPCC0_MPCC_BG_R_CR … macro
H A Ddcn_3_1_2_offset.h6475 #define regMPCC0_MPCC_BG_R_CR … macro
H A Ddcn_3_2_1_offset.h4794 #define regMPCC0_MPCC_BG_R_CR … macro
H A Ddcn_3_1_6_offset.h6695 #define regMPCC0_MPCC_BG_R_CR … macro
H A Ddcn_4_1_0_offset.h5318 #define regMPCC0_MPCC_BG_R_CR … macro