Searched refs:regMP1_SMN_IH_SW_INT_CTRL (Results 1 – 10 of 10) sorted by relevance
| /linux/drivers/gpu/drm/amd/include/asic_reg/mp/ |
| H A D | mp_14_0_0_offset.h | 289 #define regMP1_SMN_IH_SW_INT_CTRL … macro
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| H A D | mp_13_0_4_offset.h | 380 #define regMP1_SMN_IH_SW_INT_CTRL … macro
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| H A D | mp_13_0_2_offset.h | 387 #define regMP1_SMN_IH_SW_INT_CTRL … macro
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| H A D | mp_13_0_8_offset.h | 382 #define regMP1_SMN_IH_SW_INT_CTRL … macro
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| H A D | mp_15_0_0_offset.h | 366 #define regMP1_SMN_IH_SW_INT_CTRL … macro
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| H A D | mp_13_0_0_offset.h | 379 #define regMP1_SMN_IH_SW_INT_CTRL … macro
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| H A D | mp_13_0_6_offset.h | 380 #define regMP1_SMN_IH_SW_INT_CTRL … macro
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| H A D | mp_14_0_2_offset.h | 289 #define regMP1_SMN_IH_SW_INT_CTRL … macro
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| H A D | mp_13_0_5_offset.h | 381 #define regMP1_SMN_IH_SW_INT_CTRL … macro
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu15/ |
| H A D | smu_v15_0_8_ppt.c | 1180 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); in smu_v15_0_8_irq_process()
1182 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data); in smu_v15_0_8_irq_process()
1230 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); in smu_v15_0_8_set_irq_state()
1232 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); in smu_v15_0_8_set_irq_state()
1242 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); in smu_v15_0_8_set_irq_state()
1244 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); in smu_v15_0_8_set_irq_state()
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