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Searched refs:regMP1_SMN_IH_SW_INT_CTRL (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/swsmu/smu14/
H A Dsmu_v14_0.c828 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); in smu_v14_0_set_irq_state()
830 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); in smu_v14_0_set_irq_state()
871 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); in smu_v14_0_set_irq_state()
873 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); in smu_v14_0_set_irq_state()
920 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); in smu_v14_0_irq_process()
922 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data); in smu_v14_0_irq_process()
/linux/drivers/gpu/drm/amd/include/asic_reg/mp/
H A Dmp_14_0_0_offset.h289 #define regMP1_SMN_IH_SW_INT_CTRL … macro
H A Dmp_13_0_4_offset.h380 #define regMP1_SMN_IH_SW_INT_CTRL … macro
H A Dmp_13_0_2_offset.h387 #define regMP1_SMN_IH_SW_INT_CTRL … macro
H A Dmp_13_0_8_offset.h382 #define regMP1_SMN_IH_SW_INT_CTRL … macro
H A Dmp_15_0_0_offset.h366 #define regMP1_SMN_IH_SW_INT_CTRL … macro
H A Dmp_13_0_0_offset.h379 #define regMP1_SMN_IH_SW_INT_CTRL … macro
H A Dmp_13_0_6_offset.h380 #define regMP1_SMN_IH_SW_INT_CTRL … macro
H A Dmp_14_0_2_offset.h289 #define regMP1_SMN_IH_SW_INT_CTRL … macro
H A Dmp_13_0_5_offset.h381 #define regMP1_SMN_IH_SW_INT_CTRL … macro
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_6_ppt.c1830 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); in smu_v13_0_6_irq_process()
1832 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data); in smu_v13_0_6_irq_process()
1880 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); in smu_v13_0_6_set_irq_state()
1882 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); in smu_v13_0_6_set_irq_state()
1892 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); in smu_v13_0_6_set_irq_state()
1894 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); in smu_v13_0_6_set_irq_state()