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Searched refs:regMP1_SMN_IH_SW_INT (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/mp/
H A Dmp_14_0_0_offset.h287 #define regMP1_SMN_IH_SW_INT … macro
H A Dmp_13_0_4_offset.h378 #define regMP1_SMN_IH_SW_INT … macro
H A Dmp_13_0_2_offset.h385 #define regMP1_SMN_IH_SW_INT … macro
H A Dmp_13_0_8_offset.h380 #define regMP1_SMN_IH_SW_INT … macro
H A Dmp_15_0_0_offset.h364 #define regMP1_SMN_IH_SW_INT … macro
H A Dmp_13_0_0_offset.h377 #define regMP1_SMN_IH_SW_INT … macro
H A Dmp_13_0_6_offset.h378 #define regMP1_SMN_IH_SW_INT … macro
H A Dmp_14_0_2_offset.h287 #define regMP1_SMN_IH_SW_INT … macro
H A Dmp_13_0_5_offset.h379 #define regMP1_SMN_IH_SW_INT … macro
/linux/drivers/gpu/drm/amd/pm/swsmu/smu15/
H A Dsmu_v15_0_8_ppt.c1237 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT); in smu_v15_0_8_set_irq_state()
1240 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val); in smu_v15_0_8_set_irq_state()