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Searched refs:regMP1_SMN_C2PMSG_40 (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/mp/
H A Dmp_14_0_0_offset.h109 #define regMP1_SMN_C2PMSG_40 … macro
H A Dmp_13_0_4_offset.h248 #define regMP1_SMN_C2PMSG_40 … macro
H A Dmp_13_0_2_offset.h255 #define regMP1_SMN_C2PMSG_40 … macro
H A Dmp_13_0_8_offset.h202 #define regMP1_SMN_C2PMSG_40 … macro
H A Dmp_15_0_0_offset.h186 #define regMP1_SMN_C2PMSG_40 … macro
H A Dmp_13_0_0_offset.h199 #define regMP1_SMN_C2PMSG_40 … macro
H A Dmp_13_0_6_offset.h200 #define regMP1_SMN_C2PMSG_40 … macro
H A Dmp_14_0_2_offset.h109 #define regMP1_SMN_C2PMSG_40 … macro
H A Dmp_13_0_5_offset.h201 #define regMP1_SMN_C2PMSG_40 … macro
/linux/drivers/gpu/drm/amd/pm/swsmu/smu15/
H A Dsmu_v15_0_8_ppt.c2386 ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_40); in smu_v15_0_8_init_msg_ctl()