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Searched refs:regMP0_SMN_C2PMSG_81 (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dpsp_v13_0_4.c64 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); in psp_v13_0_4_is_sos_alive()
187 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), in psp_v13_0_4_bootloader_load_sos()
188 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), in psp_v13_0_4_bootloader_load_sos()
H A Dpsp_v13_0.c146 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); in psp_v13_0_is_sos_alive()
330 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), in psp_v13_0_bootloader_load_sos()
331 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), in psp_v13_0_bootloader_load_sos()
H A Dsoc21.c478 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); in soc21_need_reset_on_init()
910 sol_reg1 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); in soc21_need_reset_on_resume()
912 sol_reg2 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); in soc21_need_reset_on_resume()
/linux/drivers/gpu/drm/amd/include/asic_reg/mp/
H A Dmp_13_0_4_offset.h129 #define regMP0_SMN_C2PMSG_81 macro
H A Dmp_13_0_2_offset.h129 #define regMP0_SMN_C2PMSG_81 macro
H A Dmp_13_0_8_offset.h130 #define regMP0_SMN_C2PMSG_81 macro
H A Dmp_13_0_0_offset.h127 #define regMP0_SMN_C2PMSG_81 macro
H A Dmp_13_0_6_offset.h128 #define regMP0_SMN_C2PMSG_81 macro
H A Dmp_13_0_5_offset.h129 #define regMP0_SMN_C2PMSG_81 macro
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Daldebaran_ppt.c1972 val = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); in aldebaran_is_mode1_reset_supported()