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Searched refs:regMMVM_L2_CNTL3 (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmmhub_v3_0_2.c261 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp); in mmhub_v3_0_2_init_cache_regs()
412 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0); in mmhub_v3_0_2_gart_disable()
H A Dmmhub_v3_0_1.c262 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp); in mmhub_v3_0_1_init_cache_regs()
407 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0); in mmhub_v3_0_1_gart_disable()
H A Dmmhub_v3_0.c269 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp); in mmhub_v3_0_init_cache_regs()
420 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0); in mmhub_v3_0_gart_disable()
H A Dmmhub_v3_3.c258 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp); in mmhub_v3_3_init_cache_regs()
453 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0); in mmhub_v3_3_gart_disable()
H A Dmmhub_v4_1_0.c270 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp); in mmhub_v4_1_0_init_cache_regs()
421 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0); in mmhub_v4_1_0_gart_disable()
/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_3_3_0_offset.h658 #define regMMVM_L2_CNTL3 … macro
H A Dmmhub_4_1_0_offset.h734 #define regMMVM_L2_CNTL3 … macro
H A Dmmhub_3_0_2_offset.h744 #define regMMVM_L2_CNTL3 … macro
H A Dmmhub_3_0_0_offset.h786 #define regMMVM_L2_CNTL3 … macro
H A Dmmhub_3_0_1_offset.h1038 #define regMMVM_L2_CNTL3 … macro