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Searched refs:regMMVM_L2_CNTL (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmmhub_v3_0_2.c232 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_0_2_init_cache_regs()
243 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); in mmhub_v3_0_2_init_cache_regs()
408 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_0_2_gart_disable()
410 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); in mmhub_v3_0_2_gart_disable()
H A Dmmhub_v3_0_1.c232 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_0_1_init_cache_regs()
243 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); in mmhub_v3_0_1_init_cache_regs()
402 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_0_1_gart_disable()
404 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); in mmhub_v3_0_1_gart_disable()
H A Dmmhub_v3_0.c233 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_0_init_cache_regs()
244 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); in mmhub_v3_0_init_cache_regs()
409 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_0_gart_disable()
411 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); in mmhub_v3_0_gart_disable()
H A Dmmhub_v4_1_0.c227 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v4_1_0_init_cache_regs()
238 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); in mmhub_v4_1_0_init_cache_regs()
403 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v4_1_0_gart_disable()
405 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); in mmhub_v4_1_0_gart_disable()
H A Dmmhub_v4_2_0.c369 tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL); in mmhub_v4_2_0_mid_init_cache_regs()
383 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL, tmp); in mmhub_v4_2_0_mid_init_cache_regs()
610 tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, j), regMMVM_L2_CNTL); in mmhub_v4_2_0_mid_gart_disable()
612 WREG32_SOC15(MMHUB, GET_INST(MMHUB, j), regMMVM_L2_CNTL, tmp); in mmhub_v4_2_0_mid_gart_disable()
/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_3_3_0_offset.h654 #define regMMVM_L2_CNTL … macro
H A Dmmhub_4_1_0_offset.h730 #define regMMVM_L2_CNTL … macro
H A Dmmhub_3_0_2_offset.h740 #define regMMVM_L2_CNTL … macro
H A Dmmhub_3_0_0_offset.h782 #define regMMVM_L2_CNTL … macro
H A Dmmhub_3_0_1_offset.h1034 #define regMMVM_L2_CNTL … macro