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Searched refs:regHST_CLK0_SW1_CL0_CNTL_BASE_IDX (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_9_0_offset.h7059 #define regHST_CLK0_SW1_CL0_CNTL_BASE_IDX 5 macro
H A Dnbio_4_3_0_offset.h14985 #define regHST_CLK0_SW1_CL0_CNTL_BASE_IDX … macro
H A Dnbio_7_2_0_offset.h4725 #define regHST_CLK0_SW1_CL0_CNTL_BASE_IDX … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/nbif/
H A Dnbif_6_3_1_offset.h8622 #define regHST_CLK0_SW1_CL0_CNTL_BASE_IDX … macro