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Searched refs:regGRBM_GFX_CNTL (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsoc24.c111 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl); in soc24_grbm_select()
H A Dsoc21.c247 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl); in soc21_grbm_select()
H A Dgfx_v12_0.c705 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); in gfx_v12_0_init_rlcg_reg_access_ctrl()
2585 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); in gfx_v12_0_cp_gfx_switch_pipe()
2588 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); in gfx_v12_0_cp_gfx_switch_pipe()
H A Dgfx_v11_0.c884 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); in gfx_v11_0_init_rlcg_reg_access_ctrl()
3562 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); in gfx_v11_0_cp_gfx_switch_pipe()
3565 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); in gfx_v11_0_cp_gfx_switch_pipe()
H A Dgfx_v9_4_3.c1437 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h76 #define regGRBM_GFX_CNTL … macro
H A Dgc_9_4_2_offset.h3354 #define regGRBM_GFX_CNTL … macro
H A Dgc_11_5_0_offset.h5019 #define regGRBM_GFX_CNTL … macro
H A Dgc_12_0_0_offset.h4198 #define regGRBM_GFX_CNTL … macro
H A Dgc_11_0_3_offset.h6484 #define regGRBM_GFX_CNTL … macro
H A Dgc_11_0_0_offset.h6204 #define regGRBM_GFX_CNTL … macro