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Searched refs:regGCVM_L2_CNTL (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v12_1.c295 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regGCVM_L2_CNTL); in gfxhub_v12_1_xcc_init_cache_regs()
312 regGCVM_L2_CNTL, tmp); in gfxhub_v12_1_xcc_init_cache_regs()
568 tmp = RREG32_SOC15(GC, GET_INST(GC, j), regGCVM_L2_CNTL); in gfxhub_v12_1_xcc_gart_disable()
570 WREG32_SOC15(GC, GET_INST(GC, j), regGCVM_L2_CNTL, tmp); in gfxhub_v12_1_xcc_gart_disable()
H A Dimu_v11_0.c231 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL, 0x00080603, 0xe0000000),
314 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL, 0x00080603, 0xe0000000),
H A Dimu_v11_0_3.c83 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL, 0x00080603, 0xe0000000),
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_12_0_0_offset.h2766 #define regGCVM_L2_CNTL … macro
H A Dgc_11_0_3_offset.h2872 #define regGCVM_L2_CNTL … macro
H A Dgc_11_0_0_offset.h2730 #define regGCVM_L2_CNTL … macro