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Searched refs:regGCVM_L2_CNTL (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dimu_v11_0.c221 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL, 0x00080603, 0xe0000000),
304 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL, 0x00080603, 0xe0000000),
H A Dgfxhub_v3_0_3.c220 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL); in gfxhub_v3_0_3_init_cache_regs()
231 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp); in gfxhub_v3_0_3_init_cache_regs()
H A Dimu_v11_0_3.c83 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL, 0x00080603, 0xe0000000),
H A Dgfxhub_v11_5_0.c218 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL); in gfxhub_v11_5_0_init_cache_regs()
229 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp); in gfxhub_v11_5_0_init_cache_regs()
H A Dgfxhub_v3_0.c215 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL); in gfxhub_v3_0_init_cache_regs()
226 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp); in gfxhub_v3_0_init_cache_regs()
H A Dgfxhub_v12_0.c223 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL); in gfxhub_v12_0_init_cache_regs()
234 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp); in gfxhub_v12_0_init_cache_regs()
H A Dimu_v12_0.c242 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL, 0x00080603, 0x1c0000),
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_5_0_offset.h1859 #define regGCVM_L2_CNTL … macro
H A Dgc_12_0_0_offset.h2766 #define regGCVM_L2_CNTL … macro
H A Dgc_11_0_3_offset.h2872 #define regGCVM_L2_CNTL … macro
H A Dgc_11_0_0_offset.h2730 #define regGCVM_L2_CNTL … macro