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Searched refs:regGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h1261 #define regGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX … macro
H A Dgc_9_4_2_offset.h1120 #define regGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX … macro
H A Dgc_11_5_0_offset.h1630 #define regGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX … macro
H A Dgc_11_0_3_offset.h2621 #define regGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX … macro
H A Dgc_11_0_0_offset.h2513 #define regGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX … macro