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Searched refs:regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h801 #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h897 #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h11102 #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h11123 #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h12227 #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h1194 #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h801 #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h1398 #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h930 #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX … macro