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Searched refs:regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h815 #define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h911 #define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h11116 #define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h11137 #define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h12241 #define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h1208 #define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h815 #define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h1412 #define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h944 #define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX … macro